//
// Copyright (c) MiTAC Corp. All rights reserved.
//------------------------------------------------------------------------------
//
//  File:  clock.c
//  Programmer: Visual.Wei
//  Date: 2007-4-16
//  Description: get system clock Hz
//
#include <windows.h>
#include <oal.h>
#include <s3c2443.h>

#define FIN	12000000L

#define MPLLCON	(((volatile S3C2443_CLKPWR_REG*)OALPAtoVA(S3C2443_BASE_REG_PA_SYSCON, FALSE))->MPLLCON)
#define MDIV	((MPLLCON >> 16) & 0xff)
#define PDIV	((MPLLCON >> 8) & 0x3)
#define SDIV	((MPLLCON >> 0) & 0x1)

#define CLKDIV	(((volatile S3C2443_CLKPWR_REG*)OALPAtoVA(S3C2443_BASE_REG_PA_SYSCON, FALSE))->CLKDIV0)
#define PREDIV	((CLKDIV >> 4) & 0x3)
#define HCLKDIV	((CLKDIV>>0) & 0x3)
#define PCLKDIV	((CLKDIV>>2) & 0x1)
#define HALFHCLK	((CLKDIV>>3) & 0x1)
#define ARMDIVN ((CLKDIV >> 9) & 0xf)


#define ARMDIV				(ARMDIVN == 0 ?	1 : \
								(ARMDIVN == 8 ? 2 : \
									(ARMDIVN == 2 ? 3 : \
										(ARMDIVN == 9 ? 4 : \
											(ARMDIVN == 10 ? 6 : \
												(ARMDIVN == 11 ? 8 : \
													(ARMDIVN == 13 ? 12 : \
														(ARMDIVN == 15 ? 16 : 1) \
													) )) ) ) ) )


#define FOUT	(2 * (MDIV + 8L) * (FIN / (PDIV) / (1<<SDIV )))

#define S3C2443_FCLK	(FOUT  / ARMDIV )
#define S3C2443_HCLK	(FOUT / (PREDIV+1) / (HCLKDIV+1))   // divisor 4
#define S3C2443_PCLK	(S3C2443_HCLK / (PCLKDIV+1))  // divisor 2

UINT32 IPLGetFclk()
{
	return S3C2443_FCLK;
}

UINT32 IPLGetHclk()
{
	return S3C2443_HCLK;
}


UINT32 IPLGetPclk()
{
	return S3C2443_PCLK;
}


